Intel Xeon Phi CPU w/72 cores

Intel has upgraded it’s Xeon Phi co-processor to become a standalone CPU that can have as many as 72 cores. The older “Knights Corner” version of the Xeon Phi is a co-processor mounted on a PCIe board and can go up to 61 cores. The new “Knights Landing” version is a standalone chip that is integrated with a DDR-4 memory controller and up to 16 GBs of “in-package” RAM.

SC13: Intel reveals Knights Landing high-performance CPU – []

High-performance computing, once a niche area catering to academia and government, has become a key growth area for the tech industry as countries battle to develop the first exascale supercomputers and companies adopt the technology. Intel’s announcements at SC13 today—including new details of a completely redesigned Many Integrated Core processor—show just how important technical computing has become.


“It’s a major transition from Knights Corner,” said Raj Hazra, Vice President of the Data Center Group and General Manager of the Technical Computing Group. “You can think of Many-Core as a tock, tock, tock cadence” referring to the so-called tick-tock cadence that Intel uses to introduce major changes to its mainstream Core architecture every other year. To translate, Intel will use the extra transistors provided by Moore’s Law to make big changes.

The biggest of these is that Knights Landing will be a standalone many-core CPU that will fit into standard rack architecture and run its own operating system without needing a separate host CPU. That means Knights Landing can be used as a homogenous, many-core processor in everything from workstations to massive supercomputer clusters without having to develop for heterogeneous systems that offload certain data to accelerators.

Intel previews future ‘Knights Landing’ Xeon Phi x86 coprocessor with integrated memory – []

Intel has taken the wraps off Knights Landing, its next-gen, up-to-72-core Xeon Phi supercomputing chip. The main change is that Knights Landing will be a standalone processor, rather than a slot-in coprocessor that must be paired with standard Xeon CPU. Furthermore, Knights Landing will have up to 16GB of DRAM 3D stacked on-package, providing up to 500GB/sec of memory bandwidth (along with up to 384GB of DDR4-2400 mainboard memory). Knights Landing will debut in 2015 on Intel’s 14nm process, and with a promise of 3 teraflops (double precision) per socket it will almost certainly be used to build some monster 100+ petaflop x86 supercomputers, and beyond to exascale.

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